DRAMs (dynamic random access memories) comprise an array of memory cells, each memory cell generally comprising a transistor and a capacitor. One bit of data is memorized by each cell by storing, via the transistor, a level of electrical charge on the capacitor. The stored data is refreshed periodically.
A problem with such DRAM devices is that the capacitor is bulky and therefore it is very difficult to reduce the size of each memory cell and thus reduce the overall size of the memory or increase its capacity.
To solve this problem, alternative memory structures have been proposed, in which a memory cell comprises just a single transistor having a floating body. Thus rather than storing charge on a capacitor, charge is stored in the floating body to store data. However, the solutions that have been proposed until now are generally inadequate in terms of the retention time of each memory cell, the supply voltage requirements for writing, holding or reading data, and/or the ability of the memory cells to be used in an array.